1. Field of the Invention The present invention relates generally to a shadow RAM (Random Access Memory) cell and a non-volatile memory device employing a ferroelectric capacitor and a control method therefor. More particularly, the invention relates to a shadow RAM having a memory cell fabricated by adding a ferroelectric capacitor to a SRAM (Static RAM) cell, performing reading and writing operation at high speed in the SRAM while power is supplied, and storing data in non-volatile manner by the ferroelectric capacitor while power is not supplied.
2. Description of the Related Art
Conventionally, there have been proposed a plurality of shadow RAMs, in which the ferroelectric capacitors and the SRAM cells are combined. These shadow RAM cells store information by the SRAMs while power is supplied, for permitting high speed reading and writing comparable with common SRAM. In addition, by transferring information stored in the SRAM cells in polarizing direction of the ferroelectric capacitor before shutting down of the power source, non-volatile storage is realized. Namely, the shadow RAM employing the ferroelectric capacitor is a storage device achieving non-volatile storage ability of the ferroelectric memory and high speed operation of the SRAM.
For example, a construction of the memory cell of the shadow RAM employing the ferroelectric capacitor disclosed in Japanese Unexamined Patent Publication No. Heisei 4-57291 has a construction shown in FIG. 7. Two inverters (logical inverting elements) 1 and 2 form a flip-flop (F/F) 3 by mutually connecting input and output thereof. Tow storage nodes Q0 and Q1 of the flip-flop 3 are connected to a negative bit line BLN and a positive bit line BLT via NMOS transistors M0 and M1 serving as transfer gates respectively. These two positive and negative bit lines for a pair. To one end of a pair of positive and negative bit lines, a sense amplifier (not shown) comparing voltages thereof is connected.
Also, a writing circuit (not shown) selectively connecting either bit lines to a ground potential upon writing and a pre-charge circuit (not shown) for pre-charging the bit line to a power source potential or the ground potential are connected to the bit line. Gate electrodes of the NMOS transistors M0 and M1 are connected to a common word line WL. The word line WL is connected to a decoder circuit (not shown) for selectively driving one word line to be an object for access according to an address signal. Ferroelectric capacitors F0 and F1 connected to a common plate line PL at one end, are provided. The other ends N0 and N1 of the ferroelectric capacitors F0 and F1 are connected to the storage nodes Q0 and Q1 via NMOS transistors M2 and M3 serving as transfer gates.
Gate electrodes of the transistors M2 and M3 are connected to a common control line CL. The control line CL becomes HIGH level only during storing operation and recalling operation, in which the ferroelectric capacitors F0 and F1 are accessed, for connecting the flip-flop 3 and the ferrorelectric capacitors F0 and F1, respectively. In other states while power is supplied, the control line CL is held LOW level to electrically disconnect the flip-flop 3 and the ferroelectric capacitors. On the other hand, the plate line PL is maintained at LOW level while the control line CL is held at LOW level.
Next, operation of the conventional shadow RAM employing the ferroelectric capacitor will be discussed. It should be clear that writing and reading of information in and from the flip-flop 3 is similar to the conventionally typical SRAM. During idling while neither reading nor writing is performed, the bit line is pre-charged at HIGH level to lower potential at all word lines to disable the writing circuit and whereby to maintain information in the flip-flop 3.
For writing information in the flip-flop 3, an appropriate word line WL is risen by an address decoder. At the same time, the writing circuit is driven to make one of the bit lines BLT and BLN forming a pair into Low level according to data to write. When the word line WL i s risen, the MOS transistors M0 and M1 are turned ON. Since driving performance of the writing circuit is sufficiently larger than that of the inverters 1 and 2, the storage nodes connected to the bit lines drawn into LOW level by the writing circuit via the MOS transistor, is drawn into the ground potential. At the same time, the other storage node is pulled up to the power source voltage. Thus, the flip-flop 3 becomes stable.
On the other hand, reading of data from the flip-flop 3 is performed by selecting an appropriate word line and by amplifying a potential difference appearing on the selected bit line by the sense amplifier after pre-charging the bit line pair to HIGH level. By rising the word line WL, the MOS transistor connecting the storage node held at LOW level and the bit line, is turned ON to start lowering of the voltage of the relevant bit line. Since the MOS transistors of other bit lines are not turned ON, those bit lines are held HIGH level. By making judgment of potential difference of the bit lines forming a pair by the sense amplifier, information stored in the flip-flop can be read out.
Next, storing operation will be discussed with reference to FIGS. 8 and 9. FIG. 8 shows a hysteresis characteristics on a Q-V plane of ferroelectric capacitors F0 and F1, and FIG. 9 is a timing chart of waveforms of respective part in storing operation. Upon shutting down of the power source, data stored in the flip-flop is transferred to polarizing direction of the ferroelectric capacitors F0 and F1. This operation will be referred to as storing. Storing is activated in response to a store signal input in advance of lowering or shutting down of the power source. Storing is performed in the following procedure.
At first, the control line CL becomes HIGH level to electrically connect the flip-flop 3 and the ferroelectric capacitors F0 and F1. At this time, the plate line PL is held LOW level, 0V is applied to one of the ferroelectric capacitors connected to the storage node of 0V, and, on the other hand, a voltage of (Vcc-Vt) is applied on the side connected to the storage node of the power source voltage (Vcc). Here, Vt is a threshold voltage of the MOS transistors M2 and M3. When Vcc is applied to the control line CL, the voltage to be applied to the capacitor becomes (Vcc-Vt).
The voltages Vc0 and Vc1 respectively applied to the ferroelectric capacitors F0 and F1 are defined as potential differences between the potential on the terminal connected to the MOS transistors M2 and M3 and the potential of the terminal connected to the plate line PL. The voltage (Vcc-Vt) applied to the ferroelectric capacitor is shifted to a point A' of a hysteresis loop shown in FIG. 8.
Next, the plate line PL is risen to Vcc. At this time, the voltage applied to the ferroelectric capacitor to be applied the voltage (Vcc-Vt) at first becomes Vcc at both ends. This is because that since the transistors M2 and M3 are turned OFF to cause capacitive coupling by the ferroelectric capacitors to elevate the potential on the side of the transistor together with potential elevation of the plate line PL. Accordingly, the voltage to be applied to the ferroelectric capacitor becomes 0V to hold positive residual dielectric polarization (point B'). To the other ferroelectric capacitor, -Vcc is applied to shift to a point C of the hysteresis loop shown in FIG. 8.
Finally, the control line CL and the plate line PL are fallen down. Subsequently, the power source is shut down. After shutting down of the power source, respective nodes are converged to the ground potential. Accordingly, finally, the ferroelectric capacitor located at the point C is shifted to a point D to hold negative residual dielectric polarization. Since the ferroelectric capacitor may maintain the residual dielectric polarization for ten years or longer in the condition where no voltage is applied, the conventional shadow RAM employing the ferroelectric capacitor can store data in non-volatile manner.
Next, recall operation will be discussed with reference to the timing chart of respective part shown in FIG. 10. Upon turning ON of power source, data held by the ferroelectric capacitor is transferred to the flip-flop 3. This operation is referred to recall operation. Upon turning ON of the power source, the control line CL is fixed at low level to maintain the residual dielectric polarization of the ferroelectric capacitor. After stabilization of the power source, recall operation is initiated. At first, after pre-charging the bit line to the ground potential, the word line WL and the control line CL are risen. Subsequently, the potential of the plate line PL is risen to apply a negative voltage to the ferroelectric capacitor. At this time, one of the ferroelectric capacitors located at the point B' in FIG. 8 discharges a charge associating with inversion of polarization. The other ferroelectric capacitor located at the point D does not cause inversion of polarization to discharge smaller amount of charge. As a result, among the storage nodes Q0 and Q1, the side connected to the ferroelectric capacitor causing inversion of polarization shows higher voltage than the other.
The potential difference appearing on the storage nodes Q0 and Q1 is amplified by the sense amplifier connected to the end of the bit line and re-written to the flip-flop 3 through the writing circuit. Finally, the control line CL, the word line WL and the plate line PL are fallen down and the pre-charge circuit is disabled to complete a sequence of operation. The sequence of operation is repeatedly performed for all of the word line in the memory cell array to perform recall for all memory cells.
On the other hand, since Japanese Unexamined Patent Publication No. Heisei 1-66899 as the second prior art performs different recall operation from the first prior art whose construction is equal to that of FIG. 7, the recall operation will be discussed with reference to the timing chart of FIG. 11. In the second prior art, the power source potential of the flip-flop 3 is initially dropped to ground potential. Also, the word line WL is set at HIGH level to ground the storage node using the pre-charge circuit connected to the bit line. Then, the control line CL is set HIGH level to connect the ferroelectric capacitor to the flip-flop 3.
Then, by setting the word line WL low level, the bit line and the storage node are disconnected. Subsequently, the plate line PL is risen to HIGH level. Then, potential difference is caused in the storage nodes according to polarization direction of two ferroelectric capacitors. Thereafter, the power source potential of the flip-flop 3 is risen to the predetermined operation potential to amplify and maintain the potential difference of the storage nodes. Finally, the control line CL and the plate line PL are fallen down to be placed in idling condition.
As set forth above, in the shadow RAM employing the ferroelectric capacitors of the first and second prior art, stored data of the flip-flop 3 is maintained even through shutting down and turning ON of the power source. Therefore, the shadow RAM may serve as a non-volatile memory. Furthermore, reading and writing of data can be performed in the similar manner as normal SRAM since the flip-flop 3 and the MOS transistors M0 and M1 performs the similar function as the cell of the normal SRAM.
As the non-volatile memory employing the ferroelectric capacitor, there has been known constructions, in which the memory cell is formed with one transistor and one ferroelectric capacitor or with two transistors and two ferroelectric capacitors, as disclosed in Japanese Unexamined Patent Publication No. (Showa) 63-201998. Irrespective whether the power is supplied or not, information is stored depending upon direction of polarization of the ferroelectric capacitor. On the other hand, for destructive reading, writing can be performed subsequently to reading. Since number of times of access to the ferroelectric capacitor is quite large, reliability after use for long period cannot be always sufficient. On the other hand, in the shadow RAM employing the ferroelectric capacitor, access to the ferroelectric capacitor is performed only upon storing and recalling. Therefore, even with the ferroelectric capacitor having relatively low performance, sufficiently high reliability as product can be assured.
In the first and second conventional shadow RAMs employing the ferroelectric capacitors, the following two problems are encountered. The first problem is that number of transistors forming one memory cell is eight which is greater than normal SRAM cell (using six transistors), increasing of cell size is inherent to and thus is not suitable for achieving greater memory capacity.
The second problem is that the voltage lower than the power source voltage can be applied to the capacitor upon writing information to the ferroelectric capacitor upon shutting down of the power source. The reason is that the voltage applied to the ferroelectric capacity is restricted to (power source voltage--threshold voltage of M2 and M3). When the voltage to be applied to the ferroelectric capacitor upon storing becomes lower, the ferroelectric capacitor cannot be sufficiently polarized to cause possibility that the information cannot be restored upon turning the power source ON again. Particularly, under the trend of increasing package density of the CMOS process in the recent year, in which degree of lowering of the threshold voltage (Vt) becomes smaller than lowering of the power source voltage (Vcc), (Vcc-Vt) of the voltage in storing can cause more significant problem toward the future.
On the other hand, for applying the power source voltage without voltage drop, it becomes necessary to apply a voltage higher than the power source voltage in the extent corresponding to Vt, to the control line CL. In order to use high voltage, a circuit for generating high voltage is necessary. Secondly, it is also required to employ elements and circuits which can withstand the high voltage. Particularly, development of the transistor withstanding high voltage can be disinsentive for increasing package density of the advanced CMOS.
In addition to the foregoing two common problems, the first prior art encounters a problem in long operation period since the recall operation becomes repeated operation. Furthermore, relatively large control circuit is required for controlling the repeated operation. Namely, in the first prior art, the sense amplifier and the writing circuit are employed for recall operation. Therefore, bit number which can be recalled once is limited by number of the sense amplifiers and the writing circuits. Therefore, in recalling all memory cells, the recall operation for at least the number of word lines, is inherently repeated.